Senior DV Engineer

Job Summary:

We are looking for passionate and motivated SoC Design Verification Engineers to work on CPU-based SoC and IP verification projects. 

You will be part of a dynamic verification team contributing to pre-silicon verification using System Verilog & UVM

Key Responsibilities:

• Develop and execute Systemverilog/UVM Testbenches for SOC/IP Verification
• Develop Test plan, Implement & run directed, random, and constrained random tests
• Write C & SV/UVM based tests development & debug
• Debug simulation failures and work with RTL team for resolution.
• Functional & code coverage analysis and sign-off checklist closure.

Required Skills:

• 4-8 years of Verification experience with hands-on knowledge in SV/UVM
• Experience in ARM based SOC & IP Level Verification
• Strong working knowledge in CPU(ARM) based SOC and SOC integration concepts
• Familiarity with standard verification tools ( VCS, Xcelium) and debug environment
• Scripting skills ( Python/Perl) 
• Strong debugging, analytical and problem-solving skills 
• Experience in one of the High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)

Optional/Preferred Skills

• Exposure to Formal Verification or assertion-based verification.
• Power aware verification ( UPF)
• GLS & Xprop runs