
ASIC Formal Verification Engineer, TPU Compute
Job Description
- Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
- Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
- Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
- Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
- Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.