Back to jobs
S

Logic Design Engineer

Rancho Cordova, CA, United StatesPosted 2 months ago
Full-timehybridNot Applicable

Job Description

Join Solidigm’s visionary Design Engineering Team as a 3D NAND Logic Design Engineer and help shape the future of memory technology.

Job responsibilities include, but not limited to:

  • Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers
  • Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off
  • Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features
  • Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks
  • Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality
  • Support post-silicon debug and failure analysis across multiple configurations
  • MS in electrical or computer engineering with 5+ years of experience, or BS with 7+ years of experience
  • Hands‑on experience with micro‑controller architecture, instruction sets, and compilers, with the ability to design, implement, and debug micro‑code for memory control algorithms (read, program, erase, initialization, power‑on sequences)
  • Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO
  • Strong background in design verification tools and automation scripting
  • Prior experience in 3D NAND Flash Memory logic design is a plus
  • Ability to work independently across pre- and post-silicon debug cycles

The compensation range for this role is $105,440 - $164,800. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

This is a Hybrid role reporting out of Rancho Cordova CA; or San Jose CA. 

Powered by SmartRecruiters - Candidate Privacy Policy

See Your Match Score

Sign up and Renata will show you how this job matches your skills and experience.

Logic Design Engineer at Solidigm | Renata