Own the development and maintenance of an industry-standard ASIC implementation flow and use it to perform RTL-to-GDS2 digital physical implementation, including timing constraint generation, synthesis, floor planning, place and route, clock tree synthesis (CTS), design for test (DFT) (Scan, MBIST, BISR), static timing analysis (STA), signal/power integrity (SI/PI), layout versus schematic and design rule checking (LVS/DRC).
Collaborate with internal architecture and design team to evaluate tradeoffs of various design approaches at the power/performance/area (PPA) level.
Manage program execution of implementation of quantum control electronics ICs with internal team and external vendors, including backend execution, packaging, schedules, SOWs and documentation commits, sign-off quality metrics, foundry and post-silicon.
Contribute to IP evaluation and negotiation of IP contracts.
Contribute to ASIC vendor selection process.

Staff Silicon Physical Design Engineer

Job Description