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Job Description
- Deliver system-on-chip (SoC) Static Timing Analysis.
- Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
- Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
- Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs.