Lead the bring-up process on debugging stations, including FPGA-based platforms, upon the arrival of the first silicon. Assist in the analysis of silicon failures and collaborate with design and test engineering teams to ascertain root causes.
Advocate enhancements in the validation flow, encompassing new tools, methodologies, and scripts, to significantly boost efficiency and coverage.
Partner with the Architecture, Physical Design, and Test Engineering teams to ensure the integration and execution of the Design-for-Test (DFT) plan.
Work in close conjunction with the verification team to meticulously define test plans, formulate assertions, and debug logic issues, thereby ensuring functional correctness.

Senior Silicon Bringup and Test Lead, Raxium

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