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Job Description
- Own and execute the Register-Transfer Level (RTL) design and micro-architecture for high-performance fabrics and Network on Chip (NoC) subsystems from concept to tape-out. Run and analyze Power Performance Area (PPA) for the designs, and do design trade-offs to understand/optimize the design.
- Perform in-depth search performance analysis of NoC topologies, including latency modeling, bandwidth bottleneck identification, and arbitration tuning. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers.
- Drive front-end implementation tasks, run and debug Lint, CDC, RDC, and logical Equivalency Checks (LEC).
- Collaborate closely with physical design engineers to manually optimize floorplanning and timing closure for the fabric, ensuring high-frequency goals are met.
- Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations.