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ASIC RTL Engineer III, Silicon

Google
Bengaluru, Karnataka, IndiaPosted 2 weeks ago
hybrid
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Job Description

  • Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
  • Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
  • Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
  • Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification.
  • Communicate and work with multi-disciplined and multi-site teams.

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ASIC RTL Engineer III, Silicon at Google | Renata