Trainee Engineer - DV
Job Description
Design Verification Engineer | 2 Years Experience
2 years of experience in ASIC/SoC Design VerificationStrong hands-on experience with SystemVerilog and UVMDeveloped and maintained UVM testbenches, sequences, drivers, monitors, and scoreboardsPerformed block-level and subsystem-level verificationExperienced in test plan creation, coverage analysis (functional & code coverage), and closureWorked on debugging RTL and testbench issues using simulators (VCS / Questa / Xcelium)Good understanding of AMBA protocols (AXI / AHB / APB) (if applicable)Experience in regression runs, bug tracking, and verification sign-offCollaborated closely with design, validation, and architecture teamsFamiliar with version control (Git/Perforce) and CI/regression flowsMentored junior engineers and supported reviews
Work Experience
Key Skills
- SystemVerilog, UVM
- Functional Verification
- Coverage-driven Verification
- Debug & Root Cause Analysis
- ASIC / SoC Verification Flo