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Job Description
- Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
- Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHSIC Hardware Description Language (VHDL)), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.