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Job Description
- Oversee the physical design implementation of complex blocks, subchips, and top-level designs, ensuring technical excellence and project success.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, package) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Own and plan the physical design execution schedule, actively communicating status and risks to management.