Defect Management Engineer
Job Description
This role serves as a core technical leader responsible for end‑to‑end defect engineering—from advanced SiC defect reduction and AI‑based inspection operations to SPC‑driven yield and reliability improvement—bridging UPS, Defect Management, and Fab organizations from technology development through mass production.
Key Responsibilities & Scope
(1) SiC Technology Advancement and New Defect Mode Improvement
- Defect density reduction activities for various onsemi SiC products, including
SiC MOSFETs, Super Junction structures, multi‑epitaxial growth, and Trench Gate devices - Root cause analysis and improvement activities for surface defects, trench‑inside defects, sub‑CD micro defects, and Killer / Slow Killer defects
(2) ADC & Klarity Operation and Production / VOG Management
- Production operation of AI‑based Defect Classification (ADC) systems
- ADC retraining, critical step monitoring, and troubleshooting
- Defect management for production and VOG (Visual Outgoing Inspection)
Key Roles and Organizational Needs
(1) Focus on AOI / Defect Engineering
- Operation of AOI inspection equipment
(Maintenance, EVT, and recipe optimization) - Product‑level defect engineering support for BK Factory
- Defect 대응 for new products and transferred products
(2) Advanced Defect Engineering Expertise
- Acting as a senior defect engineering expert with strong experience in understanding defect characteristics by product family
- Driving specialization and technical depth within the Defect Engineering organization
End‑to‑End Support from Technology Development to Mass‑Production Ramp‑up
(1) New Process Introduction Phase
- Prediction of potential defect modes
- Definition of inspection schemes
- Selection of inspection tools and collaboration with vendors
(2) Mass Production Phase
- Leading SPC‑based defect density management
- Driving yield and reliability improvement activities
- Serving as a core technical leader connecting UPS, Defect Management, and Fab organizations
This role serves as a core technical leader responsible for end‑to‑end defect engineering—from advanced SiC defect reduction and AI‑based inspection operations to SPC‑driven yield and reliability improvement—bridging UPS, Defect Management, and Fab organizations from technology development through mass production.
Key Responsibilities & Scope
(1) SiC Technology Advancement and New Defect Mode Improvement
- Defect density reduction activities for various onsemi SiC products, including
SiC MOSFETs, Super Junction structures, multi‑epitaxial growth, and Trench Gate devices - Root cause analysis and improvement activities for surface defects, trench‑inside defects, sub‑CD micro defects, and Killer / Slow Killer defects
(2) ADC & Klarity Operation and Production / VOG Management
- Production operation of AI‑based Defect Classification (ADC) systems
- ADC retraining, critical step monitoring, and troubleshooting
- Defect management for production and VOG (Visual Outgoing Inspection)
Key Roles and Organizational Needs
(1) Focus on AOI / Defect Engineering
- Operation of AOI inspection equipment
(Maintenance, EVT, and recipe optimization) - Product‑level defect engineering support for BK Factory
- Defect 대응 for new products and transferred products
(2) Advanced Defect Engineering Expertise
- Acting as a senior defect engineering expert with strong experience in understanding defect characteristics by product family
- Driving specialization and technical depth within the Defect Engineering organization
End‑to‑End Support from Technology Development to Mass‑Production Ramp‑up
(1) New Process Introduction Phase
- Prediction of potential defect modes
- Definition of inspection schemes
- Selection of inspection tools and collaboration with vendors
(2) Mass Production Phase
- Leading SPC‑based defect density management
- Driving yield and reliability improvement activities
- Serving as a core technical leader connecting UPS, Defect Management, and Fab organizations
Qualifications
(1) Experience
- Minimum 4 years of experience in Defect Engineering or Defect Management within semiconductor factory or process environments
- Position level: Engineer to Senior Manager (Grade 10–14); compensation based on HR policy and experience
(2) Technical Capability
- Proven ability to lead the resolution of chronic defects and Killer / Slow Killer defect issues
(3) Communication Skills
- Ability to communicate effectively in English with global sites
(OPIc, TOEIC Speaking, or equivalent level per HR standards) - Strong communication and collaboration skills across internal and cross‑functional organizations
More details about our company benefits can be found here: