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Job Description
- Contribute to DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
- Develop and drive DFT validation strategy for the SoC and Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
- Integrate and connect MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
- Execute Post Silicon ATE Bring up and sustenance and Lead complete DFT phase at wafer Level.