Lead the definition of power requirements for Tensor mobile System-on-Chips (SoCs) to achieve Power-Performance-Area (PPA) with a primary focus on the memory subsystem (memory controller, DDRPHY, DRAM).
Own and drive cross-functional teams to deliver on power Key Performance Indicators (KPIs) for the memory subsystem and other major SoC IPs.
Propose and drive power optimizations for the memory subsystem throughout the design process from concept to mass productization.
Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
Represent status of SoC power to the executive leadership team.

SoC Power Lead, Memory Subsystem

Job Description