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Job Description
- Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG).
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.