DV IP Lead

The IP DV Lead is a "deep-diver." This role focuses on the exhaustive verification of a specific functional block (e.g., a Crypto engine, Video Codec, or High-Speed Controller), ensuring 100% functional and code coverage within that domain.

Core Responsibilities

Block-Level Strategy: Create comprehensive testplans based on IP functional specifications to reach 100% functional coverage.

Environment Development: Build highly constrained-random UVM environments, including agents, monitors, and complex scoreboards.

Formal Verification: Apply formal methods (SVA) to verify complex state machines or data paths where simulation falls short.

Bug Hunting: Identify corner-case bugs through assertions and functional coverage-driven stimulus.

Regression Management: Maintain high-efficiency regression suites and lead the closure of code, functional, and toggle coverage.

Collaboration: Work closely with RTL designers to resolve architectural ambiguities and debug RTL failures.

Required Skills & Qualifications

Experience: 8+ years in IP-level functional verification.

Technical Mastery: Advanced SystemVerilog/UVM and expertise in writing complex SVA (SystemVerilog Assertions).

Domain Expertise: Specific knowledge of the IP being verified (e.g., USB, Ethernet, or AI accelerators).

Methodology: Strong background in Constrained Random Verification (CRV) and coverage-driven sign-off.

Scripting: Proficiency in Python or Perl for testbench automation and log parsing.