Job Description
This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Design Verification Engineer based in United States.
This role sits at the core of advanced semiconductor and communications technology development, focusing on ensuring the correctness, reliability, and performance of complex ASIC and FPGA designs.
It involves building and evolving sophisticated verification environments that validate RTL implementations across high-performance hardware systems.
You will work closely with design, systems, and software engineering teams to define verification strategies, coverage goals, and test methodologies.
The position leverages modern verification frameworks such as UVM, alongside emerging AI-driven verification tools to accelerate and enhance chip validation.
You will be responsible for end-to-end verification ownership, from planning and testbench development to debugging and coverage closure.
This is a highly technical, hands-on role in a fast-paced engineering environment focused on cutting-edge communications technologies.
It is ideal for an experienced verification engineer who thrives on complex problem-solving and system-level thinking.
This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Design Verification Engineer based in United States.
This role sits at the core of advanced semiconductor and communications technology development, focusing on ensuring the correctness, reliability, and performance of complex ASIC and FPGA designs.
It involves building and evolving sophisticated verification environments that validate RTL implementations across high-performance hardware systems.
You will work closely with design, systems, and software engineering teams to define verification strategies, coverage goals, and test methodologies.
The position leverages modern verification frameworks such as UVM, alongside emerging AI-driven verification tools to accelerate and enhance chip validation.
You will be responsible for end-to-end verification ownership, from planning and testbench development to debugging and coverage closure.
This is a highly technical, hands-on role in a fast-paced engineering environment focused on cutting-edge communications technologies.
It is ideal for an experienced verification engineer who thrives on complex problem-solving and system-level thinking.
