Back to jobs
Job Description
- Lead and manage functional Static Timing Analysis (STA) team responsible for delivering system-on-chip (SoC) STA.
- Execute full chip timing sign-off checklist, perform full chip STA, power recovery, timing ECO creation and oversee final timing sign-off for SoC’s.
- Define SoC timing sign-off process corners, derates, uncertainties and their trade-offs.
- Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area.
- Collaborate with front-end, Design for Test (DFT) and Computer-aided design (CAD) teams for the design exploration and closure.