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Job Description
- Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
- Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out.
- Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers.
- Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations.