
Senior CPU Design Verification Engineer, Emulation
Job Description
- Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis.
- Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches.
- Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation.
- Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers.
- Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues.