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Job Description
- Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
- Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
- Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
- Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
- Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.