Staff Engineer, CPU Architectural Verification

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will own CPU architectural verification, shaping how our out-of-order RISC-V CPUs are validated against architectural intent, ISA behavior, privileged architecture requirements, and system-visible correctness across the verification stack.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who You Are 

• You bring 8+ years in CPU architectural verification, CPU design verification, or closely related CPU validation work.
• You understand CPU ISA behavior, privileged architecture, exception handling, memory ordering, and high-performance out-of-order CPU microarchitecture in depth.
• You are comfortable debugging architectural mismatches using RTL, waveforms, logs, reference models, and complex test scenarios.
• You have experience developing or applying architecture-focused stimulus, checkers, or validation strategies across simulation and emulation environments.
• You communicate clearly across architecture, design, DV, emulation, and post-silicon teams.

 

What We Need 

• Plan and drive architectural verification for CPU core features, ISA behavior, privileged architecture flows, and system-visible microarchitectural scenarios.
• Develop and execute architecture-focused verification content using UVM, assembly, C/C++, directed tests, and constrained-random stimulus.
• Build and refine architectural checkers, scoreboards, coverage models, and reference-model-based validation flows to track and close architectural coverage.
• Debug simulation and emulation regressions by isolating architectural failures, root-causing RTL versus model mismatches, and driving closure with design and verification teams.
• Develop and debug functional models of RISC-V extensions and CPU-adjacent components relevant to architectural correctness and integration.
• Improve core, cluster, and chip-level testbenches and infrastructure to better support architectural bring-up, debug, and coverage closure.
• Support design bring-up across simulation, emulation, and post-silicon environments, with a focus on architectural correctness and debug scalability.

 

What You Will Learn 

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techniques for spanning architectural verification across pre-silicon, emulation, and post-silicon environments with shared stimulus and debug workflows.
• Ways to scale architectural coverage, checker infrastructure, and debug methodologies across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

 

 

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.