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Job Description
- Manage IP vendors for standard cell libraries, SRAM compilers, GPIO, eFuse, OT, and process sensors.
- Analyze architecture and design specifications to drive new circuit designs, including standard cells and memory options, to meet stringent Performance, Power, Area (PPA) and cost goals on process nodes.
- Collaborate with foundry and test-chip teams to validate the functionality and characterization of new circuit topologies.
- Negotiate design and timelines with 3PIP vendors, engaging in technical and schedule trade-off discussions.
- Provide technical support to Architecture, Design, and Physical Design teams to optimize the use of foundation IPs for improved functionality and PPA.