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Job Description
- Define and own the Chip/IP architectures for next-generation ML accelerators.
- Lead the architecture and design of the chip top-level, managing interfaces, clocking, power, and integration of all major IP blocks.
- Architect specific accelerator components and chiplets.
- Collaborate with micro-architecture and physical design teams to ensure a feasible and optimal design, making trade-offs in performance, power, and area (PPA).
- Work with systems and software teams to ensure the SoC architecture meets product requirements.