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Senior Design Verification Engineer, Multimedia/AI/ML, Silicon
Posted Today
Job Description
- Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process.
- Plan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios.
- Work with architecture, software, design, and back-end implementation stakeholders to make technical decisions.
- Create and enhance constrained-random verification environments using system verilog and UVM. Identify and implement improvements to the verification methodologies.
- Identify verification gaps and demonstrate advancement towards tape-out through comprehensive coverage metrics. Debug tests with design engineers to deliver functionally correct design blocks.