Develop and port Transaction-Level Modeling (TLM)/functional models for SoC subsystems, focus on network (Wi-Fi/modem) and memory accelerators (data compression).
Apply knowledge of embedded CPUs, networking protocols, and operating system memory management (zram/zswap) to model pipelines and data flows.
Implement and verify models using SystemC, Quick Emulator (QEMU), or gem5, ensuring correctness in packet processing and compression transactions.
Simulate accelerator interactions with host CPUs and memory via Advanced eXtensible Interface (AXI)/Advanced Peripheral Bus (APB) protocols.
Debug system models and leverage driver development experience for early hardware/software co-verification and software stack execution.

Pre-Silicon Performance Architect, Modeling and Analysis

Job Description