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Job Description
- Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that strictly adhere to PPA targets, coding standards, and quality guidelines.
- Manage the full RTL lifecycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis.
- Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.
- Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure.
- Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.