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Job Description
- Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.