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Job Description
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Develop and maintain constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).
- Create and execute verification plans and test cases. Identify and debug verification failures.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
- Integrate any verification IP for externally developed IP into our overall verification flow.