PD Senior Engineer

Hardware Physical Design Engineer

Google G Chips is seeking experienced Physical Design Engineers to drive the implementation and optimization of next-generation SoC designs. The role involves owning key aspects of the physical design flow and delivering high-quality silicon that meets aggressive Power, Performance, and Area (PPA) targets.

Key Responsibilities:

• Drive physical design activities including floorplanning, Place & Route (PnR), Clock Tree Synthesis (CTS), and timing closure.
• Perform PPA optimization and resolve timing, congestion, and power-related challenges.
• Develop and validate timing constraints and perform Static Timing Analysis (STA).
• Execute and debug LEC, VCLP, and EMIR signoff checks.
• Collaborate with cross-functional teams to achieve design and tapeout milestones.

Required Skills:

• Strong experience in ASIC/SoC Physical Design and implementation.
• Expertise in PnR, CTS, STA, timing convergence, timing constraints, and PPA optimization.
• Hands-on experience with LEC, VCLP, and EMIR analysis.
• Cadence Innovus experience is mandatory.
• Experience with Synopsys Fusion Compiler is also acceptable.
• Strong debugging, problem-solving, and communication skills.

Preferred:

• Experience with advanced technology nodes (7nm and below).
• Scripting knowledge in Tcl, Perl, or Python.

Location: Taiwan

Experience: 5+ Years

Keywords: Physical Design, PnR, CTS, Timing Closure, STA, PPA, Floorplanning, Innovus, Fusion Compiler, LEC, VCLP, EMIR, ASIC, SoC.