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Job Description
- Lead effort for timing constraint creation and validation, timing analysis and timing Engineering Change Order (ECO) creation, and final timing sign-off for complex ASICs.
- Drive both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
- Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
- Interface with the broader team to triage and resolve reported technical issues, escalating complex tool-related problems to Electronic Design Automation (EDA) vendors and deliver timely and effective solutions.
- Lead collaboration with RTL design and DFT team for high quality integrations and timing constraints.
