Trainee Engineer - DV

Role: Trainee Engineer

Ensure chip design works correctly before fabrication (no bugs, meets requirements).

Key Responsibilities

• Create test plans and test cases for design validation [vlsifirst.com]
• Develop testbenches (SystemVerilog/UVM) to simulate design behavior [velvetjobs.com]
• Run simulations and debug issues in RTL/design [semivlsi.com]
• Analyze coverage to ensure all scenarios are tested [semivlsi.com]
• Identify and fix functional bugs before tape-out [maven-silicon.com]
• Work closely with design/RTL engineers and architects [careers.ti.com]

Basic Skills

• SystemVerilog / UVM
• Digital design fundamentals
• Debugging & problem solving
• Knowledge of protocols (AXI, APB, etc.)

• SystemVerilog / UVM
• Digital design fundamentals
• Debugging & problem solving
• Knowledge of protocols (AXI, APB, etc.)