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Job Description
- Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA) and formal tools.
- Debug tests with design engineers to deliver design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
- Identify and write all types of coverage measures for stimulus and corner-cases.