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Job Description
Purpose of this Position
深入研究高速訊號，在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質
Major Areas of Responsibility
專案研發
- Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5.
- Perform pre-layout, layout constraint, and post-layout simulation processes.
- PCB stackup design and layout review for high speed signal and PDN.
- Build component models to ensure the correlation between SI/PI simulation and measurement.
- Solid SI experience in resolving technical issues and performing detailed analysis.
團隊合作
- Collaborating with EE teams to refine high-speed signal performance.
- Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.
Minimum Job Requirements
Education:研究所(含)以上
Experience:
Must have an MS in EE related field.
- Experience with signal and power integrity analysis tools (ex: Ansys HFSS, Ansys SIWAVE, Cadence Clarity, Cadence Sigrity, Keysight ADS, Intel ICAT etc).
- Experience with Intel chip design, including knowledge of related technologies and specifications.
- Comprehensive knowledge of SI/EMI/EMC/Transmission Line theory and applications.
- Skilled in Allegro constraints and tools.
- Experience with measurement equipments (ex: TDR, VNA) is a plus.
- Experience with Matlab, Python, or C for simulation automation is a plus.
Language: 中文、英文
Required Competencies
- 負責、主動、誠實、熱忱,、有執行力，具有很好的跨部門溝通協作及團隊合作能力。
- 有能力獨立完成問題分析、確認及提出解決方案解決問題。
- 學習能力強、有良好的邏輯判斷能力。
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