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Browse fresh roles from company career pages, then filter by keyword, location, salary, skills, remote scope, and more. Each listing links back to the employer-controlled apply path when available.
Browse fresh roles from company career pages, then filter by keyword, location, salary, skills, remote scope, and more. Each listing links back to the employer-controlled apply path when available.
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios. Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test cover
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM). Identify and write all types
Debug tests with design engineers to deliver functionally correct design blocks. Perform integration checks like connectivity. Write tests in SystemVerilog (SV) and assembly/C. Perform SoC Boot, configuration and data path verification at SoC level. Participate in design debug, c
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage; ensure docu
Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or for
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or forma
Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or for
Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and Universal Verifi
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or forma
Plan the verification of digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios. Develop and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or
Qorvo, Inc.
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves
LitePoint
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation sol
LitePoint
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation sol
OMNIVISION
Description Description: As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-s
Rambus
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional
Lattice Semiconductor
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operat
Bolt Graphics
Principal Design Verification Engineer Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce t
Synopsys Inc
Job Title HBM Design Verification Engineer, Sr Staff Job ID 14002 Country Taiwan City Hsinchu Date Posted 13-Jan-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No
Synopsys Inc
Job Title Sr Staff, ASIC Design Verification Engineer-13965 Job ID 13965 Country Canada City Kanata State/Province Kanata Date Posted 09-Jan-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No
Synopsys Inc
Job Title Principal ASIC Design Verification Engineer-16988 Job ID 16988 Country Canada City Nepean State/Province Nepean Date Posted 14-Apr-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No
Synopsys Inc
Job Title Senior/Staff Design Verification Engineer Job ID 16078 Country Viet Nam City Ho Chi Minh Date Posted 09-Mar-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No