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Job Description
- Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tape-out signoff criteria to ensure successful multi-voltage implementation.
- Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools (e.g., Synopsys VCLP) to ensure power/ground integrity and UPF alignment.
- Drive the resolution of complex Physical Design and Place and Route (P&R) anomalies, specifically mitigating issues such as wrong domain buffering, secondary power routing failures, and isolation clamping errors.
- Perform targeted debugging on advanced Clock Tree Synthesis (CTS) implementations, analyzing tool behavior around level shifters in high fanout networks, duty cycle distortions, and multi-voltage skew management.
- Drive the continuous refinement of power state tables (PST) and Unified Power Format (UPF) scripts to ensure accurate translation from Golden RTL to the final physical netlist.