Sr. Hardware Validation & Integration Engineer

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:

What You Will Do:

The Hardware Validation & Integration Engineer is responsible for ensuring the reliability, performance, and qualification of complex digital hardware systems. This role spans signal integrity testing and analysis, hardware bring‑up, environmental validation, cross‑functional debugging, and sustaining engineering support. The engineer will collaborate closely with firmware, FPGA, manufacturing, and system integration teams to drive high‑quality hardware releases from prototype through production.

• Perform signal integrity (SI) testing, digital timing analysis, and interface‑level validation for high‑speed digital subsystems.
• Create detailed test plans, validation procedures, and qualification reports for hardware subsystems.
• Oversee the build, maintenance, and continuous updates of hardware targets used for product development and verification.
• Debug hardware failures, perform root‑cause analysis, and collaborate with cross‑functional leads to drive closure.
• Support line‑down or field‑returned issues by reproducing failures, validating fixes, identifying component‑level or design‑level issues. and qualifying repaired units.
• Perform bay‑level and target‑level testing to validate interoperability, performance, and reliability.
• Execute temperature cycling, vibration testing, and other environmental stress tests to validate design robustness.
• Analyze results, identify failure modes, and recommend corrective actions to improve long‑term reliability.
• Update derating analysis, digital timing analysis, thermal assessments, and hardware design documents.
• Support firmware and FPGA teams with hardware configuration, board setup, and programming workflows. Assist in debugging hardware‑dependent firmware issues and validating new firmware drops on hardware targets.
• Drive engineering change requests (ECR/ECO) through internal release systems (Myworkshop) and coordinate with stakeholders.

Signal Integrity and Hardware qualification Testing — Performing SI testing and digital timing analysis for IMB2 and IDB2, including simulation reviews and interface‑level validation, Hydra pass2 board qualifications, documenting test results and releasing in Myworkshop

FW/FPGA Hardware Support — Supporting FW/FPGA teams with hardware‑related changes/setup as required, PCIe programming via ChipLink, FPGA programming using Quartus with latest released versions on the ICE2 targets and updating PLL configurations as required.

Target Build & Maintenance — Oversee the building, maintenance, and continuous updates of ICE2 hardware targets to support product development and verification activities. This includes running RDT tests and updating the daily tracker, executing HAST tests, logging issues in Jira, and coordinating with cross‑functional leads to ensure timely assignment and closure. Additionally, responsible for debugging ICE2 hardware issues and supporting teams in resolving any hardware‑related failures.

Qualification & Bay Testing — Performed qualification testing of ICE FPGAs Release 6 at targets and bays. Performed Qualification testing of Gen3 ISUs and Gen3 Exciters, Supported ICE DUART line down issues by testing and qualifying ICE units at target and bays.

Environmental Testing — Executing temperature and vibration testing of SSC subsystems (Gen3 ISUs and Exciters) in the environmental lab to validate the new design changes.

MR Manufacturing and IB support to SSC subsystems — Debugging SSC subsystems as required, including field‑failed HART ID dongles and IB‑returned failed units, and driving corrective actions.

Component & Documentation Updates — Created test plans to perform SI testing and TPR of IMB2, IDB2 and Hydra boards, updated thermal and component derating analyses, currently revising HDDs for IMB2/IDB2, testing LTB components (PCIE cable, CTS OCXO oscillator) and driving ECR/ECO releases through MyWorkshop in coordination with sourcing and HW integrators.

System Integration Testing — Supported the Rhea team with 1‑Wire system integration testing (EEPROM) and validating subsystem behavior across multiple configurations.

What You Will Bring:

• Bachelor’s or master’s degree in electrical/electronic engineering, or related field.
• Strong experience with high‑speed digital design technique, signal integrity, and hardware validation.
• Hands‑on experience with oscilloscopes, logic analyzers, protocol analyzers, and SI tools.
• Proficiency with FPGA toolchains like Quartus and hardware programming workflows.
• Experience with environmental testing methodologies and reliability engineering principles.
• Ability to debug complex hardware issues at board and system level.
• Strong documentation, communication, and cross‑functional collaboration skills.
• Experience with automated test frameworks and scripting like Python
• Knowledge of high‑speed interfaces (PCIe, DDR, etc.).
• Experience with change‑management systems and hardware release processes.

Pay Range: ($80K- $95K

Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.