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Job Description
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform RTL development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Participate in architecture feedback.