SiC Yield Enhancement Engineer

The SiC Yield Enhancement Senior Engineer is responsible for improving SiC manufacturing yield, solving process and defect issues, and supporting stable production ramp-up. The role requires hands-on analysis, cross-functional teamwork, and strong technical understanding of semiconductor processes.

Key Responsibilities:

• Analyze SiC yield data, identify root causes, and drive corrective actions. 
• Conduct DOE, engineering experiments, and statistical evaluations to improve process robustness. 
• Resolve defect, leakage, and EOS-related issues with failure analysis support. 
• Collaborate closely with Device, UPD, Equipment, QA, and Manufacturing to implement process improvements. 
• Support customer quality requirements by reducing process risks and preparing audit-related documentation. 
• Utilize JMP/MINITAB and fab data to monitor performance and drive data-based decisions.

Required Qualifications:

• Bachelor’s degree or higher in Engineering (Materials, Chemical, Electrical, Mechanical).
• 5–10 years of experience in semiconductor yield, process integration, or defect engineering (SiC preferred).
• Strong skills in DOE, SPC, statistical analysis tools, and semiconductor process fundamentals.
• Experience with defect/failure analysis and electrical characterization.
• Strong communication and teamwork abilities. 

Preferred Qualifications:

• Experience in TCAD modeling/simulation and layout/tape-out processes. 
• Familiarity with wafer-level and product-level reliability testing. 
• Programming skills for automation and data analysis are a plus.