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Job Description
- Plan the verification of complex digital design blocks within the ISP, DPU, or CODEC subsystems by thoroughly analyzing specifications and collaborating with design engineers to identify key verification scenarios.
- Design, build, and maintain constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
- Develop comprehensive functional coverage plans and implement them to track verification progress.
- Debug failures in simulation, identify root causes in RTL or testbenches, and work with designers to resolve issues.
- Define and run regression suites, analyze coverage metrics, and drive verification closure towards tape-out.