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Job Description
- Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration.
- Define and develop RTL implementations that meet power, performance and area goals.
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.