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Job Description
- Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
- Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
- Define and implement various coverage measures to capture stimulus and corner-case scenarios.
- Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
- Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.