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Job Description
- Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform RTL development (coding and debug in Verilog, SystemVerilog).
- Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
- Contribute to verification test plan and coverage analysis of block and SoC-level.