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Job Description
- Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
- Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
- Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
- Engage in CDC and RDC tool setup, analysis, triage and design changes.
- Define and document the microarchitecture for complex digital designs within the TPU. Contribute to the development and enhancement of design tools, flows, and methodologies.