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Teradyne

Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)

North Reading, MAPosted Today

Job Description

  • Lead and mentor a team of physical design engineers across the full project lifecycle
  • Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
  • Develop and own chip floorplans, timing budgets, power estimates, and pin planning
  • Partner with design teams to develop high-quality SDC constraints
  • Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
  • Support hands-on place-and-route (P&R) for critical and high-speed blocks
  • Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
  • Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
  • Ensure robust signoff closure including DRC/LVS and EM/IR analysis
  • Develop, enhance, and maintain physical design tool flows and automation
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    5001-10000 employees
    North Reading, MA, US
    Website
    Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA) at Teradyne | Renata