Back to jobsOwn and execute the full layout lifecycle for analog and mixed‑signal IP blocks such as ADCs, DACs, PLLs, LDOs, bandgaps, amplifiers, and pixels.
Collaborate closely with circuit design engineers to understand specifications, constraints, and performance trade-offs.
Develop floorplans, layout strategies, and routing plans that optimize matching, noise performance, EM/IR robustness
Perform custom layout of critical analog circuits using industry‑standard EDA tools (e.g., Cadence Virtuoso).
Ensure compliance with design rules (DRC), electrical rules (ERC), layout-vs-schematic checks (LVS), and parasitic extraction (PEX).
Drive layout quality through guard‑ringing, shielding, isolation techniques, symmetry enforcement, and dummy placements.
Work with foundry PDKs to interpret process rules, device models, and reliability requirements (ESD, EM, latch‑up).
Generate and maintain layout documentation, checklists, and layout guidelines for internal use.
Prepare designs for tapeout, including final checks, documentation, and coordination with the fabrication team.
Develop and maintain scripts to automate repetitive tasks, improving efficiency and consistency in the design process.
Participate in technical reviews with design team and customer.
Able to work independently and collaborate with local technical lead.
