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Job Description
- Monitor, analyze, and improve package-level yields for 2.5D/3D architectures. Track yield from known good die and interposer testing through final assembly and Class/System-Level Test.
- Identify and root-cause major yield detractors. Use statistical tools to correlate final package failures back to wafer-level testing, substrate defects, or assembly process variations.
- Act as the primary technical interface with foundries and OSATs. Drive suppliers on process control monitors, recipe optimizations, and corrective actions for assembly-induced defects.
- Characterize complex, multi-chip module failure mechanisms. Coordinate destructive and non-destructive Failure Analysis (FA) techniques.
- Feed post-silicon yield and FA learning back to the Design for Manufacturing and Design for Test teams to improve next-generation Chip-on-Wafer-on-Substrate (CoWoS)/Embedded Multi-die Interconnect Bridge (EMIB) product architectures.