Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
Insert DFT logic, including scan chains, MBIST, Test Access Port (TAP) controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, electronic fuse (eFuse) logic and connect to core and TAP interfaces.
Design Verification of DFT logic and test pattern generation.
Design and Implement System Level Test strategy.

DFT Engineer, Google Cloud

Job Description