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Job Description
- Design and implement DSP algorithms for high-speed PHYs, focusing on feed-forward equalization (FFE)/decision feedback equalization (DFE) and timing recovery loops.
- Perform fixed-point analysis to minimize bit-width (area/power) while maintaining the required signal-to-noise ratio (SNR).
- Develop bit-exact C++/SystemC models to verify register-transfer level (RTL) against architectural intent.