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Job Description
- Define and document the Design for Testability (DFT) architecture for multi-core System on Chips (SoCs), including strategies for hierarchical scan compression, MBIST (Memory BIST), Logic BIST and Analog Mixed Signal circuits.
- Implement DFT logic, boundary scan, MBIST, scan chains, DFT compression, Clock Control block, and other DFT Internet Protocol (IP) blocks.
- Work with the Register Transfer Level (RTL) and Physical Design (PD) team at SoC level, and with the subsystem DFT teams.
- Write scripts to automate the DFT flow.
- Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow.